In recent years, a demand for a high-speed large-capacity (high-density) data transmission technique has been increased in a field of HPC (High Performance Computing) of high-end servers and super computers. However, in general electric transmission techniques, increase of speed and capacity has limitations and it may be difficult to realize data transmission capability (in terms of speed and a bandwidth) requested by HPC systems. As a breakthrough technique for limitation of the electric transmission techniques, an optical interconnect technique for transmitting data using light has been drawing the attention.
A photodiode of a receiver used in a high-speed optical interconnect technique preferably has a light-receiving diameter which is formed as large as possible in terms of optical connection to an optical transmission path (an optical fiber, a polymer optical waveguide, and the like). However, a photodiode (hereinafter referred to as a “PD” where appropriate) having a large light-receiving diameter has large capacitance in proportion to a light-receiving area, and therefore, the photodiode does not respond to a high-speed signal.
As a method of expanding a band of such a PD having a large light-receiving diameter, peaking using an inductor has been used. An optical electric (OE) converter included in a frontend of a light receiver includes a PD which converts a component of incident light into a current and a trans-impedance amplifier (TIA) which converts a micro current generated in the PD into a voltage. However, it is difficult to form the PD and the TIA in the same process on the same substrate.
When the PD and the TIA are connected to each other using a bonding wire, the bonding wire may be used as a peaking inductor. However, it is difficult to control an inductance of the bonding wire and speeding up has limitations. This is because, as a frequency becomes high, impedance increases, and high-frequency signals are difficult to pass.
In the high-speed optical interconnect, PD chips and a TIA chip are connected to each other through transmission paths by flip-chip implementation. However, it is difficult to ensure physical spaces for implementing inductors corresponding to PDs in the transmission paths. Therefore, the inductors are preferably formed in the PD chips.
Here, a technique of forming an inductor making use of a diffusion region included in a semiconductor device has been known. Related techniques are disclosed in Japanese Laid-open Patent Publication Nos. 62-244160 and 2003-179146, for example.
In FIG. 1A, an end portion of an inductor line 102 disposed on a resistive layer 103 and an end portion of a metal line 105 connected to a transistor, are connected to an n+ type diffusion layer 104 which is formed in a semiconductor substrate 101. The n+ diffusion layer 104 enables ohmic contact between the inductor line 102 and the resistive layer 103 and ohmic contact between the metal line 105 and the resistive layer 103. In FIG. 1B, a p-type diffusion layer 205 is formed in a spiral manner in an N-well 203 included in a silicon substrate 201 so as to form an inductor, and the inductor is connected to lines 209 and 211 through via contacts 207.
However, in a general PD process, a PIN (p-intrinsic-n) configuration is formed by epitaxial grown, and therefore, the general PD process does not include an injection process. When the methods illustrated in FIGS. 1A and 1B are employed in generation of an inductor of a PD, an injection process is additionally performed.